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Relaxed is OK if the target is a single-core device
for a multi-core device AcqRel ordering for the fetch-add operation and Release ordering for the store operation would have been required for correctness
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@@ -192,13 +192,12 @@ main thread without disabling interrupts. When possible, this is a better
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solution — but it may not be supported on your platform.
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A note on [`Ordering`]: this affects how the compiler and hardware may reorder
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instructions, and also has consequences on cache visibility. For simple atomic
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operations like incrementing a counter, where we are not synchronising any
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other tasks on the counter, `Relaxed` is sufficient, and will have the best
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performance on typical embedded platforms. Stricter ordering will cause the
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compiler to emit memory barriers around the atomic operations; depending on
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what you're using atomics for you may or may not need this! The precise
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details of the atomic model are complicated and best described elsewhere.
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instructions, and also has consequences on cache visibility. Assuming that the
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target is a single core platform `Relaxed` is sufficient and the most efficient
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choice in this particular case. Stricter ordering will cause the compiler to
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emit memory barriers around the atomic operations; depending on what you're
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using atomics for you may or may not need this! The precise details of the
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atomic model are complicated and best described elsewhere.
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For more details on atomics and ordering, see the [nomicon].
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